Computer graphics systems are special purpose computers that are used to create complex images on a display and to allow the computer user to modify and store the images.
Showing images on a display and moving the images on the display screen is a complex computer task, and there is a need in the industry for methods for more efficiently performing this complex task. In addition, as computer graphics applications become more popular, there is a need in the industry for computer graphics systems that are less expensive than current systems.
Many of the elements of a typical computer graphics system are shown in FIG. 4 of U.S. Pat. No. 4,745,407, entitled "Memory Organization Apparatus and Method", issued May 17, 1988 to Costello. A graphics accelerator is a special purpose processor unit which receives graphics commands from the CPU and executes them, typically by changing information stored in the frame buffer. A frame buffer is a special purpose type of memory in which the memory locations correspond to a location, or pixel, on a color monitor, or other type of display. Devices not shown in FIG. 4 of Costello sequentially read the memory locations in the frame buffer, and cause the pixel to be lit with the appropriate intensity or color, thereby causing the image to be shown on the display.
In addition to the elements shown in Costello, some computer graphics systems may have a CPU cache memory. A Cache memory is a memory placed in close proximity to the CPU, and which contains the information in main memory locations most frequently accessed by the CPU. The close proximity of cache memory enable the CPU to more quickly access the data in the cache memory than can the CPU access the data in the main memory.
A typical cache memory system consists of cache RAM (random access memory), a cache controller, and a tag store. The tag store is a table of the main memory addresses of the information that is stored in the cache RAM. The cache RAM stores the information that is operated on by the CPU. The cache controller controls the information that passes in and out of the cache RAM, and updates the cache tag store. The specific structure of the cache tag store and of the entries in a cache tag store are dependent on whether a cache is a "direct mapped" cache, a "set associative" cache, or a "fully associative" cache. More details can be found in computer architecture textbooks, such as "Computer System Architecture" by M. Morris Mano, Prentice-Hall, Inc., Englewood Cliffs, N.J., 1982. One characteristic of all cache tag stores, however, is that they have some method for indicating the main memory addresses corresponding to the entries in the cache memory.
When the CPU needs the information in a main memory address, the tag store is searched for the main memory address. If the main memory address is in the tag store (a cache "hit"), the information is retrieved from the cache RAM and sent to the CPU. If the main memory address is not in the tag store (a cache "miss"), the cache controller retrieves the information from main memory, stores it in cache RAM, and records the main memory address in the tag store. When the CPU stores the information, it sends the information back to the cache controller, which stores the information in the cache RAM. If the cache is a "writethrough" cache, the information is also written to the corresponding address in main memory. If the cache is a "writeback" cache, the information is not written to the corresponding address in main memory until a later time.
In a computer system, it is important that the contents of any location in main memory is identical to all system components that access main memory. If a main memory location is in cache memory, particularly a "writeback" cache memory, the information in main memory may not be the most current value, and the information in main memory must be updated before any system component other than the CPU attempts to read that main memory location. Verifying whether or not a main memory location is resident in cache, and updating the value can be done in a number of ways, but many of them result on some traffic on the system bus, even if the main memory location is not currently resident in cache.
Similarly, if any system component other than the CPU writes to a main memory location, there must be some method of verifying if that location is in cache, and if it is, to update the information in cache. This can be done in a number of ways, but all result in some traffic on the system bus, even if the memory location is not currently resident in cache.